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LAS VEGAS--(BUSINESS WIRE)--June 18, 2001--Sagantec of Fremont Calif. today announced SiClone, the industry's first automatic full-custom layout migration design tool that preserves design hierarchy -- permitting for the first time the use of automatic migration in existing design flows.

SiClone accelerates physical implementation of existing high performance digital, analog or mixed-signal custom integrated circuits in new advanced fabrication technologies (0.18 micron to 0.1 micron) by re-using the physical architecture and topology of the circuit's existing layout. The new tool automatically creates layouts that are comparable to handcrafted results produced by traditional manual migration methods. Integrated in a complete design flow, SiClone also optimizes layouts to reach more aggressive performance targets.

``In the past, full-custom layout design has been a bottleneck for companies that need to migrate custom designs such as processors, Flash memory or mixed-signal chips to new process technologies,'' said Hein van der Wildt, president and CEO of Sagantec. ``With SiClone, our customers have been able to reuse existing designs and automatically migrate them rapidly to new technologies, producing results that match the quality and density of handcrafted designs. SiClone helps our customers optimize physical designs to achieve more aggressive performance targets for high-performance digital cores. With SiClone, our customers can also create and evaluate a physical design concurrent with semiconductor process development, significantly shortening the lead time from technology to product.''

SiClone Features

With its simultaneous, n-level hierarchy compaction engine, SiClone is unique in its ability to maintain the hierarchical structure of a circuit during the migration process. By preserving design hierarchy, SiClone is able to provide results that can be reused in incremental or iterative design and verification flows. Prior to SiClone, earlier migration techniques produced flat designs or designs with limited hierarchy -- incompatible with hierarchical representations used in other phases of design.

``In the past, attempts to migrate a GDSII layout to produce a manufacturable GDSII layout in another technology would change the hierarchical structure, thus preventing its use in design flows,'' said Maarten Berkens, Sagantec's CTO. ``SiClone supports simultaneous multi-level hierarchy compaction that maintains the full hierarchical structure of a design, so that the data is consistent with schematic and netlist representations used in the design flow. As a result, SiClone can be integrated easily in physical, functional and timing verification flows, and the SiClone generated layout can be used in any step of the design and re-used for future designs.''

In migrating an existing full-custom design, SiClone reads an existing layout and adjusts the physical design to the new technology rules and design constraints -- creating a correct and optimized new physical implementation. SiClone performs automatic device sizing, enabling full-custom design closure. To handle process and layout changes, SiClone's automatic device sizing capability provides a means to adjust transistor drive strength to close timing and address power and noise issues. In addition, the tool will also adjust the number of contact cuts to the new device size for optimal strapping of well and substrate ties and guard-rings.

SiClone also supports design closure and performance optimization for new designs. SiClone works with static timing or timing simulators to validate timing of all critical paths. When timing violations are detected, SiClone adjusts transistor sizes on critical paths to help meet timing requirements. For performance optimization, SiClone performs automatic layout adjustment using adjusted device sizes provided by circuit optimization tools.

Able to work seamlessly with the Cadence design environment, SiClone can directly access the Cadence DFII database, avoiding the need to stream GDSII data between SiClone and other design tools. SiClone recognizes and maintains all DFII design properties, constraints, and attributes.

Availability

SiClone will be available in the third quarter of this year for Solaris and HP-UX platforms with time-based license pricing starting at $225,000/year. SiClone supports GDSII and Cadence DFII.

About Sagantec

Sagantec provides software, methodologies and services that enable rapid implementation reuse and design closure for full custom physical designs in sub-wavelength technologies. The company is working closely with its semiconductor partners and customers to ensure that its products work with technologies of 0.13 micron and below. Sagantec products are specifically designed to accelerate the physical design process of high performance/low power CPUs, and DSPs, dedicated and embedded memories, and analog/mixed-signal circuits. Privately held and funded, Sagantec was founded in 1993 in Israel. Its Corporate headquarters for sales, marketing, technical services and applications organization is located at 46485 Landing Parkway, Fremont, Calif. 94538. Telephone: 510/360-5200. Facsimile: 510/360-5255. On the web at: http://www.sagantec.com.

Note to Editors: Sagantec acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

     Sagantec North America
     Coby Zelnik, 510/360-5200 ext. 110
     coby@sagantec.com
     http://www.sagantec.com
        or
     Lee Public Relations
     Pam Wasserman, 650/363-0142
     pam@leepr.com